Memory device configured to store and output address in response to internal command

ABSTRACT

A memory device includes first and second bank groups, an internal command generator, and an address input/output circuit. Each of the bank groups includes a plurality of banks. The internal command generator generates and outputs internal commands to a first target bank. The internal commands are generated based on a command from a memory controller for controlling a memory operation of the first target bank. The address input/output (I/O) circuit receive a first address corresponding to the command, selects a storage path of the first address based on whether there is a bubble interval in a data burst operation interval corresponding to the first command, controls output of the first address in accordance with a time point at which each of the internal commands is output. The first address is stored in the address I/O circuit.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2017-0146178, filed on Nov. 3, 2017,and entitled, “Memory Device Configured to Store and Output Address inResponse to Internal Command and Method of Operating the Memory Device,”is incorporated by reference herein in its entirety.

BACKGROUND 1. Field

One or more embodiments described herein relate to a memory device tocontrol the storage and output of an address in response to an internalcommand.

2. Description of the Related Art

Semiconductor memory devices are widely used in high-performanceelectronic systems. One example is a dynamic random-access memory, whichis a volatile memory that determines data values based on charges storedin capacitors. In addition, a variety of memory systems have beenproposed for writing and reading large amounts of data at high speed.These memory systems may operate based on a reference clock frequency,which is different from a data clock frequency used to transceive databetween memory devices and a memory controller. However, there may bedrawbacks to using reference and data clock frequencies.

SUMMARY

In accordance with one or more embodiments, a memory device includes afirst bank group; a second bank group, each of the first and second bankgroups including a plurality of banks; an internal command generator togenerate a first internal command and a second internal command based ona first command from a memory controller, the first command to control amemory operation of a first target bank in the first bank group, theinternal command generator to output the first internal command and thesecond internal command to the first target bank; and an addressinput/output (I/O) circuit to receive a first address corresponding tothe first command, select a storage path of the first address based onwhether there is a bubble interval in a data burst operation intervalcorresponding to the first command, control output of the first addressin accordance with a time point at which each of the first internalcommand and the second internal command is output, and store the firstaddress in the address I/O circuit.

In accordance with one or more other embodiments, a memory deviceincludes a first bank group; a second bank group, each of the first andsecond bank groups including a plurality of banks; an internal commandgenerator to generate a first internal command and a second internalcommand based on a first command received from a memory controller, thefirst command to control a memory operation of a first target bank ofthe first bank group, generate a third internal command based on asecond command received from the memory controller to control a memoryoperation of a second target bank of the second bank group after thefirst command, and output the first to third internal commands; and anaddress input/output (I/O) circuit to receive the first to thirdinternal commands, receive from the memory controller a first addresscorresponding to the first command and a second address corresponding tothe second command, and store the first address and the second addressusing a storage path selected based on whether the third internalcommand is received, within a first clock cycle from a time point atwhich the first internal command is received.

In accordance with one or more other embodiments, a memory deviceincludes a first bank group; a second bank group, each of the first andsecond bank groups including a plurality of banks; an internal commandgenerator to generate a first internal read command and a secondinternal read command, based on a first read command received from amemory controller and output the first and second internal read commandsto a first target bank of the first bank group; and an addressinput/output (I/O) circuit including a first latch and a second latch,the address I/O circuit to receive from the memory controller a firstaddress corresponding to the first read command and store the firstaddress in the first latch based on the first internal read command. Theaddress I/O circuit is to select the first latch in which the firstaddress is stored based on whether a bubble interval is detected in adata burst operation interval corresponding to the first read commandand output the first address stored in the first latch to the firsttarget bank in accordance with a time point at which the internalcommand generator outputs the second internal read command to the firsttarget bank.

In accordance with one or more other embodiments, a non-transitorycomputer-readable medium comprising code, which, when executed by aprocessor, causes the processor to generate, by an internal commandgenerator, a first internal command and a second internal command basedon a command from a memory controller, the command to control a memoryoperation of a first target bank in a first bank group; receive, by anaddress input/output (I/O) circuit, a first address corresponding to thecommand; select a storage path of the first address based on whetherthere is a bubble interval in a data burst operation intervalcorresponding to the command; control output of the first address inaccordance with a time point at which each of the first internal commandand the second internal commands is output to the first target bank; andstore the first address in the address I/O circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Features will become apparent to those of skill in the art by describingin detail exemplary embodiments with reference to the attached drawingsin which:

FIG. 1 illustrates an embodiment of a memory system;

FIG. 2 illustrates another embodiment of a memory system;

FIG. 3 illustrates an embodiment of a memory device;

FIG. 4 illustrates an embodiment which includes first and second bankgroups;

FIG. 5A illustrates an embodiment of signals for controlling a memorydevice, and FIG. 5B illustrates an embodiment of the memory device whichmay be controlled by the signals of FIG. 5A;

FIG. 6A illustrates an embodiment of a memory operation of a memorydevice, and FIG. 6B illustrates an embodiment of a memory deviceperforming the memory operation of FIG. 6A;

FIG. 7 illustrates an embodiment of an address input/output (I/O)circuit;

FIG. 8 illustrates an embodiment of a bubble interval detector;

FIG. 9 illustrates an embodiment of a depth address output circuit;

FIG. 10A illustrates an embodiment for controlling the storage andoutput of a first address of a depth-based address output unit whenthere is a bubble interval in a data burst interval corresponding to afirst command, and FIG. 10B illustrates an embodiment of a timingdiagram for operating the depth-based address output unit of FIG. 10A;

FIG. 11A illustrates an embodiment for controlling the storage andoutput of a first address of a depth-based address output unit when abubble interval is not in a data burst interval corresponding to a firstcommand, and FIG. 11B illustrates an embodiment of a timing diagram foroperating the depth-based address output unit of FIG. 11A;

FIGS. 12A and 12B illustrate embodiments of timing diagrams foroperating a memory device in a read operation;

FIG. 13 illustrates an embodiment of an address I/O circuit thatoperates in consideration of a read operation devoid of a read latency;

FIG. 14 illustrates another embodiment of a bubble interval detector;

FIG. 15 illustrates an embodiment of a depth-based address output unit;

FIG. 16 illustrates another embodiment of a depth-based address outputunit;

FIG. 17 illustrates another embodiment of a memory system;

FIG. 18 illustrates an embodiment of a semiconductor package; and

FIG. 19 illustrates another embodiment of a semiconductor package.

DETAILED DESCRIPTION

FIG. 1 illustrates an embodiment of a memory system 10A which mayinclude a memory controller 100A and a memory device 200A. The memorycontroller 100A may include a memory interface 110A. The memorycontroller 100A may provide various signals through the memory interface110A to the memory device 200A and control memory operations, such as awrite operation and a read operation. For example, the memory controller100A may provide commands CMD and addresses ADDR to the memory device200A and access data DATA of the memory region 210A. Also, the memorydevice 200A may transceive data DATA through a DQ pad or a DQ pinbetween the memory controller 100A and the memory device 200A.

The memory controller 100A may access the memory device 200A upon arequest from a host HOST. The memory controller 100A may communicatewith the host HOST using various protocols. For example, the memorycontroller 100A may communicate with the host HOST using an interfaceprotocol, such as peripheral component interface-express (PCI-E),advanced technology attachment (ATA), serial ATA (SATA), parallel ATA(PATA), or serial attached SCSI (SAS). In addition, one of various otherinterface interfaces, such as a universal serial bus (USB), amulti-media card (MMC), an enhanced small disk interface (ESDI), or anintegrated drive electronics (IDE), may be applied to the interfaceprotocol between the host HOST and the memory controller 100A.

The memory device 200A may include a memory region 210A, an internalcommand generator 220A, and an address I/O circuit 230A. The memoryregion 210A may include a plurality of bank groups BG. Each of the bankgroups BG may include a plurality of banks. In an embodiment, each ofthe banks may include a memory cell array, a row decoder, a columndecoder, and a sense amplifier. The memory device 200A may be dynamicrandom-access memory (DRAM), such as double-data-rate synchronous DRAM(DDR SDRAM), low-power double-data-rate (LPDDR) SDRAM, graphics doubledata rate (GDDR) SDRAM, and Rambus DRAM (RDRAM).

The frequency of a reference clock that used as a basis for a memoryoperation of the memory device 200A may be lower than a frequency of adata clock that is used as a basis for a data burst operation of thememory device 200A. Specifications of the memory system 10A may conform,for example, to standard protocols established by the Joint ElectronDevice Engineering Council (JEDEC).

Due to a frequency difference between the reference clock and the dataclock, an interval (e.g., a bubble interval) in which data DATA is nottransceived to and from a DQ pad may occur during a memory operation(e.g., a data burst operation corresponding to a command) of the memorydevice 200A. To improve efficiency of the memory operation andperformance of the memory system 10A, the memory system 10A may performa memory operation for reducing or minimizing a bubble interval. Forexample, the memory device 20A may perform the memory operation on eachof a plurality of bank groups BG. The address I/O circuit 230A may storean address ADDR to perform the memory operation on each of the bankgroups BG, and may perform a first-in-first-out (FIFO) control operationto output the stored address ADDR in an appropriate time point.

The internal command generator 220A may generate internal commands basedon a command CMD from the memory controller 100A. In an embodiment, whenthe burst length of a data burst operation performed by the memorydevice 200A based on the command CMD is a predetermined number ofreference bits or more, the internal command generator 220A may generateat least two internal commands. For example, the internal commandgenerator 220A may generate a first internal command and a secondinternal command when the burst length of the data burst operationcorresponding to the command CMD is 2n bits (n is an integer equal to ormore than 2) equal to or more than the reference bits.

The burst length of a data burst operation corresponding to each of thefirst internal command and the second internal command may be n bits. Asdescribed above, by generating the internal commands using the internalcommand generator 220A, when a data burst operation having a burstlength of a predetermined number of reference bits or more is to beperformed, the memory device 200A may divide the burst length into burstlengths having a prescribed number of reference bits or less and performthe data burst operation. Furthermore, the internal memory device 220Amay operate in an on-the-fly (OTF) mode and perform the data burstoperation by varying the burst length.

Assuming that the internal command generator 220A receives the commandCMD and generates the first internal command and the second internalcommand, the address ADDR corresponding to the command CMD may be outputto the bank group BG twice in accordance with a time point at which thefirst internal command is output to the bank group BG and a time pointat which the second internal command is output to the bank group BG.

To control output of the address ADDR, the address I/O circuit 230Aaccording to an embodiment may store the address ADDR from the memorycontroller 100A, and output the address ADDR to the bank group BG inaccordance with a time point at which an internal command generated bythe internal command generator 220A is output to the bank group BG. Theaddress I/O circuit 230A may select a storage path of the address ADDRbased on whether there is a bubble interval in a data burst operationinterval corresponding to the received command CMD.

The address I/O circuit 230A may control a circuit that stores anaddress ADDR when there is the bubble interval in the data burstoperation interval corresponding to the received command CMD to bedifferent from a circuit that stores the address ADDR when there is notthe bubble interval. The address I/O circuit 230A may output the storedaddress ADDR to the bank group BG in accordance with a time point atwhich the internal command is output to the bank group BG. Due to theabove-described operations of the address I/O circuit 230A, the bubbleinterval may be reduced. As a result, the memory device 200A may performefficient memory operations.

FIG. 2 illustrates an embodiment of a memory system 10B which mayinclude an application processor (AP) 100B and a memory device 200B. Amemory control module 110B in the AP 100B and the memory device 200B mayform a memory system. Also, the memory device 200B may include a memoryregion 210B, an internal command generator 220B, and an address I/Ocircuit 230B.

The AP 100B may function as the host HOST of FIG. 1. Also, the AP 100Bmay be embodied by a System on Chip (SoC), which may include a systembus to which predetermined standard bus protocols are applied andvarious intellectual properties (IPs) connected to the system bus. Anadvanced microcontroller bus architecture (AMBA) protocol available fromAdvanced RISC Machine (ARM) Ltd. may be applied as a standard protocolof the system bus. Examples of bus types to which the AMBA protocol isapplied include Advanced High-Performance Bus (AHB), Advanced PeripheralBus (APB), Advanced eXtensible Interface (AXI), AXI4, and AXI CoherencyExtensions (ACE). In addition, other types of protocols, such asuNetwork available from SONICs Inc, CoreConnect available from IBM, andan OCP-IP Open-Core Protocol, may be applied.

The memory control module 110B may serve the same function as the memorycontroller of the previous embodiment. Also, the memory device 200B mayperform a memory operation for reducing or minimizing a bubble intervalthat may occur due to a difference between a frequency of a referenceclock (used for the memory operation) and a frequency of a data clock(used for a data burst operation). The address I/O circuit 230B maystore the address ADDR and output the address ADDR in an appropriatetime point to support the memory operation.

FIG. 3 illustrates an embodiment of a memory device 300 which mayinclude control logic 310, an address I/O circuit 320, a bank controllogic 330, a plurality of bank groups 340_1 to 340_n, and a data I/Obuffer 350. The memory device 300 of FIG. 3 is only an example. In oneembodiment, the memory device 300 may further include various types ofcircuits for performing write, read, and/or other memory operations.

The control logic 310 may include a command decoder 312, a mode register314, and an internal command generator 316. The control logic 310 maycontrol overall operations of the memory device 300. The command decoder312 may decode an externally applied command CMD and internally generatea decoded command signal. In an example, the command decoder 312 maydecode a chip selection signal /CS, a row address strobe signal /RAS, acolumn address strobe signal /CAS, a write enable signal /WE, and aclock enable signal CKE. Furthermore, the control logic 310 may decodean address ADDR and generate control signals associated with a writecommand or a read command. The mode register 314 may set an internalregister based on a mode register signal for designating an operationmode of the memory device 300 and the address ADDR.

The internal command generator 316 may generate an internal commandINTN_CMD based on the decoding result of the command decoder 312. In anembodiment, the internal command generator 316 may generate at least oneinternal command INTN_CMD based on a burst length of a data burstoperation based on the command CMD. The control logic 310 may output theinternal command INTN_CMD to the bank groups 340_1 to 340_n and theaddress I/O circuit 320.

The address I/O circuit 320 may include a bubble interval detector 322and a depth-based address output unit 324. The bubble interval detector322 may detect a bubble interval in a data burst operation intervalcorresponding to the command CMD. Within a first clock cycle from a timepoint at which the memory device 300 receives a command CMD forcontrolling a memory operation of a target bank of any one bank group(e.g., a first bank group 340_1), the bubble interval detector 322 maydetect a bubble interval based on whether the memory device 300 receivesanother command for controlling a memory operation of a target bank ofanother bank group (e.g., a second bank group 340_2).

For example, when the command for controlling the memory operation ofthe target bank of the second bank group 340_2 is received within thefirst clock cycle from the time point at which the command CMD forcontrolling the memory operation of the target bank of the first bankgroup 340_1 is received, the bubble interval detector 322 may generate adetection signal indicating that the bubble interval is not detected.When the command for controlling the memory operation of the target bankof the second bank group 340_2 is received after the first clock cycle,the bubble interval detector 322 may generate a detection signalindicating that the bubble interval is detected.

The bubble interval detector 322 may directly receive the command CMDand detect a bubble interval based on a pattern of the command CMD. Inanother embodiment, the bubble interval detector 322 may receive theinternal command INTN_CMD and detect the bubble interval based on apattern of the internal command INTN_CMD.

The depth-based address output unit 324 may select and store a storagepath of the address ADDR based on the detection signal generated by thebubble interval detector 322. The depth-based address output unit 324may include a plurality of depth address output circuits for storingvarious addresses and sequentially outputting the respective addressesstored therein. For example, the depth-based address output unit 324 mayinclude first to third depth address output circuits, which maysequentially output the respective addresses stored therein. Thedepth-based address output unit 324 may store a first address, which isfirstly received, in the first depth address output circuit, store asecond address, which is subsequently received, in the second depthaddress output circuit, and output the first address prior to the secondaddress.

However, as described above, since the memory device 300 generates atleast two internal commands INTN_CMD based on the command CMDcorresponding to a data burst operation having a burst length ofreference bits or more and performs a memory operation based on the atleast two internal commands INTN_CMD, the address I/O circuit 320 mayoutput an address ADDR at least twice and control the output of theaddress ADDR in accordance with time points when the internal commandsINTN_CMD are output. Also, as described above, since the memory device300 may perform a memory operation capable of reducing or minimizing thebubble interval, the depth-based address output unit 324 may control astorage path of the address ADDR based on a command pattern or aninternal command pattern to support the memory operation.

The address I/O circuit 320 may output a row address X_ADDR, a columnaddress Y_ADDR, and a bank address BA_ADDR in accordance with a timepoint at which the internal command INTN_CMD is output to the bankgroups 340_1 to 340_n of the control logic 310. In an embodiment, thebank address BA_ADDR may include addresses of the bank groups 340_1 to340_n and addresses of target banks of the bank groups 340_1 to 340_n.The bank control logic 330 may receive the bank address BA_ADDR andgenerate a bank control signal BA_CS. Banks in each of the bank groups340_2 to 340_n may receive an internal command INTN_CMD, a row addressX_ADDR, a column address Y_ADDR, and a bank control signal BA_CS in asimilar manner to the banks 340_11 to 340_1 k in the first bank group340_1. A target bank in any one of the bank groups 340_1 to 340_n may beenabled based on the bank control signal BA_CS.

A memory operation based on the internal command INTN_CMD may beperformed on memory cells in a target bank corresponding to the rowaddress X_ADDR and the column address Y_ADDR.

The data I/O buffer 350 may read data DATA from the target bank andprovide the data DATA to the outside (e.g., the memory controller 100Ain FIG. 1) of the memory device 300. In one embodiment, the data I/Obuffer 350 may receive data DATA from the outside (e.g., the memorycontroller 100A in FIG. 1) and provide the data DATA to the target bank.The data DATA may be transceived to or from the outside through a DQ padDQ. Also, the data I/O buffer 350 may perform a data burst operation andtransceive the data DATA based on an externally received data clock.

FIG. 4 illustrates an embodiment of the first bank group 340_1 and thesecond bank group 340_2 of FIG. 3. Referring to FIG. 4, the first bankgroup 340_1 may include first to k-th banks 340_11 to 340_1 k, and thesecond bank group 340_2 may include first to k-th banks 340_21 to 340_2k. A first bank 340_11 of the first bank group 340_1 may include a bankarray 341 in which a plurality of memory cells are arranged in rows andcolumns, a row decoder 342, a sense amplifier 343, and a column decoder344.

Each of the row decoder 342 and the column decoder 344 may receive abank control signal BA_CS and be enabled. The row decoder 342 and thecolumn decoder 344 may receive a row address X_ADDR and a column addressY_ADDR, respectively, and access at least one memory cell selected for amemory operation based on the row address X_ADDR and the column addressY_ADDR. For example, one bank may be selected from among banks in anyone of the bank groups 340_1 to 340_k based on the bank address BA_ADDRof FIG. 3, and memory cells of the selected bank may be addressed basedon the row address X_ADDR and the column address Y_ADDR. Theconfiguration of the first bank 340_11 of FIG. 4 may also be applied toother banks 340_12 to 340_2 k.

In at least one embodiment, a memory unit including at least one bankmay be considered as a bank group. A data I/O line may be shared amongbanks in one bank group. As shown in FIG. 4, an I/O line to input andoutput data may be shared among a plurality of banks in one bank group.The banks 340_11 to 340_1 k of the first bank group 340_1 may beconnected to a first data I/O line DIOL_1, and the banks 340_21 to 340_2k of the second bank group 340_2 may be connected to a second data I/Oline DIOL_2. Thus, by connecting a different data I/O line to each bankgroup, the memory device 300 of FIG. 3 may perform a memory operation oneach bank group.

A time interval based on a core cycle for the memory device 300 of FIG.3 to perform a memory operation based on one internal command maycorrespond to a first clock cycle in at least one embodiment. Forexample, a first internal command and a second internal commandgenerated based on a command received to control a memory operation of atarget bank of the first bank group 340_1 may be output to the targetbank in consideration of the first clock cycle. Also, a time interval ofa bubble interval (or a data burst operation interval corresponding toan internal command) may correspond to second clock cycle. However, thefirst clock cycle and the second clock cycle may be adjusted to variousclock time durations in consideration of delays of internal signals ofthe memory device 300.

FIG. 5A illustrates an embodiment of a timing diagram for operating amemory device 400, which illustrates a bubble interval B_INTV. FIG. 5Bis a block diagram of the memory device 400, illustrating an operationof an address I/O circuit 420 when a bubble interval is detected.

In accordance with one embodiment, the frequency of a data clock WCK maybe twice the frequency of a reference clock CLK, a first clock cycle maybe four clocks, and a second clock cycle may be two clocks. An outputtime interval (hereinafter, referred to as a time_CAS to CAS delay(tCCD) interval INTV_tCCD) between internal commands generated based onone command may be the first clock cycle. In one embodiment, a writelatency ‘WR latency’ may be two clocks. The frequencies and/or clockcycles may be different in other embodiments.

Referring to FIGS. 5A and 5B, the memory device 400 may receive a firstwrite command WR1 and a first address ADDR1 for controlling a memoryoperation of a first target bank 440_11 of a first bank group 440_1 in atime point t1. A burst length BL 32 of a data burst operationcorresponding to the first write command WR1 may be 32 bits. The firstaddress ADDR1 may include a first bank address BA1 corresponding to thefirst target bank 440_11 of the first bank group 440_1, a first rowaddress X1, and a first column address Y1. The internal commandgenerator 416 may generate a first internal write command INTN_WR1_a anda second internal write command INTN_WR1_b based on the first writecommand WR1. A burst length BL 16 of a data burst operationcorresponding to each of the first internal write command INTN_WR1_a andthe second internal write command INTN_WR1_b may be 16 bits.

The internal command generator 416 may output the first internal writecommand INTN_WR1_a to the first target bank 440_11 in a time point t3 inconsideration of the write latency ‘WR latency’, and output the secondinternal write command INTN_WR1_b to the first target bank 440_11 in atime point t7, which is a tCCD interval INTV_tCCD after the time pointt7. In this case, the address I/O circuit 420 may output the firstaddress ADDR1 to the first target bank 440_11 in each of the time pointst3 and t7 in accordance with the time points when the internal commandgenerator 416 output the first internal write command INTN_WR1_a and thesecond internal write command INTN_WR1_b to the first target bank440_11.

The memory device 400 may perform a data burst operation BL 16A_1corresponding to the first internal write command INTN_WR1_a between thetime point t3 and the time point t5. Afterwards, the memory device 400may perform a data burst operation BL 16A_2 corresponding to the secondinternal write command INTN_WR1_b between the time point t7 and the timepoint t9. As a result, during a time interval between t3 and t9 that isa data burst operation interval corresponding to the first write commandWR1, the bubble interval B_INTV may occur for a time interval between t5and t7 and a time interval between t9 and t11 in which a data burstoperation is not performed.

In an embodiment, the address I/O circuit 420 may detect the bubbleinterval B_INTV and store and output the first address ADDR1 based on adetection result. The address I/O circuit 420 may detect the bubbleinterval B_INTV based on whether another internal write command isreceived within a first clock cycle (or after a second clock cycle) froma time point at which the first internal write command INTN_WR1_a isreceived. When the address I/O circuit 420 detects the bubble intervalB_INTV, the address I/O circuit 420 may store the first address ADDR1 ina circuit corresponding to a first depth Dep1 to output the firstaddress ADDR1 in the time point t3, which is a write latency ‘WRlatency’ after the time point t1, and store the first address ADDR1 in acircuit corresponding to a second depth Dep2 to output the first addressADDR1 again in the time point t7. The address I/O circuit 420 mayfirstly output the first address ADDR1 through a circuit correspondingto the first depth Dep1 and then output the first address ADDR1 througha circuit corresponding to the second depth Dep2.

FIG. 6A illustrates an embodiment of a timing diagram for a memoryoperation of a memory device 400. FIG. 6B illustrates an embodiment ofthe memory device 400, illustrating an operation of an address I/Ocircuit 420 when a bubble interval is not detected.

Referring to FIGS. 6A and 6B, the memory device 400 may receive a firstwrite command WR1 and a first address ADDR1 for controlling a memoryoperation of a first target bank 440_11 of a first bank group 440_1 in atime point t1, and receive a second write command WR2 and a secondaddress ADDR2 for controlling a memory operation of a second target bank440_22 of a second bank group 440_2 in a time point t3. For example,when the memory device 400 may receive the second write command WR2within a first clock cycle from a time point at which the first writecommand WR1 is received. The first write command WR1 and the firstaddress ADDR1 may be as described above with reference to FIG. 5A.

A burst length BL 32 of a data burst operation corresponding to thesecond write command WR2 may be 32 bits. In accordance with oneembodiment, the burst length BL 32 of the data burst operationcorresponding to the second write command WR2 may be 16 bits or anothernumber of bits.

The internal command generator 416 may output a third internal writecommand INTN_WR2_a to the second target bank 440_22 in a time point t5in consideration of a write latency ‘WR latency’, and output a fourthinternal write command INTN_WR2_b to the second target bank 440_22 in atime point t9, which is a tCCD interval INTV_tCCD after the time pointt5. In this case, the address I/O circuit 420 may output the secondaddress ADDR2 to the second target bank 440_22 in each of the timepoints t5 and t9 in accordance with the time points when the internalcommand generator 416 outputs the third internal write commandINTN_WR2_a and the fourth internal write command INTN_WR2_b to thesecond target bank 420_22.

The memory device 400 may perform a data burst operation BL_16B_1corresponding to the third internal write command INTN_WR2_a between thetime point t5 and the time point t7. Thereafter, the memory device 400may perform a data burst operation corresponding to the fourth internalwrite command INTN_WR2_b between the time point t9 and the time pointt11. As a result, the bubble interval B_INTV detected in FIG. 5A may befilled with data burst operations BL 16B_1 and BL 16B_2 correspondingrespectively to the third internal write command INTN_WR2_a and thefourth internal write command INTN_WR2_b.

In an embodiment, for example, when the address I/O circuit 420 receivesthe third internal write command INTN_WR2_a within a first clock cyclefrom a time point at which the address I/O circuit 420 receives thefirst internal write command INTN_WR1_a, the bubble interval B_INTN maynot be detected. When the bubble interval B_INTV is not detected asdescribed above, the address I/O circuit 420 may store the first addressADDR1 in a circuit corresponding to a first depth Dept to output thefirst address ADDR1 in the time point t3, which is after the writelatency ‘WR latency’ from the time point t1, and store the secondaddress ADDR2 in a circuit corresponding to a second depth Dep2 tooutput the second address ADDR2 in the time point t5, which is after thewrite latency ‘WR latency’ from the time point t3.

Also, the address I/O circuit 420 may store the first address ADDR1 in acircuit corresponding to a third depth Dep3 to output the first addressADDR1 again in the time point t7, and store the second address ADDR2 ina circuit corresponding to a fourth depth Dep4 to output the secondaddress ADDR2 again in the time point t9. The address I/O circuit 420may output the first address ADDR1 through the circuit corresponding tothe first depth Dep1, output the second address ADDR2 through thecircuit corresponding to the second depth Dep2, output the first addressADDR1 through the circuit corresponding to the third depth Dep3, andoutput the second address ADDR2 through the circuit corresponding to thefourth depth Dep4.

FIGS. 5A to 6B illustrate only the operations of the memory device 400based on the first and second write commands WR1 and WR2. In oneembodiment, memory device 400 may operate based on a read command.

FIG. 7 illustrates an embodiment of an address I/O circuit 500 which mayinclude a bubble interval detector 510, a depth-based address outputunit 530, and an enable/reset signal generator 550. The bubble intervaldetector 510 may receive internal commands INTN_CMDs and detect bubbleintervals based on patterns of the internal commands INTN_CMDs. Thebubble interval detector 510 may generate a detection signal BD_RS basedon a detection result of the bubble intervals and provide the detectionsignal BD_RS to the depth-based address output unit 530.

The depth-based address output unit 530 may include first to n-th depthaddress output circuits 530_1 to 530_n. Each of the depth address outputcircuits 530_1 to 530_n may store any one of addresses ADDRs. Also, therespective depth address output circuits 530_1 to 530_n may correspondto different depths and output addresses, which are sequentially storedbased on the depths, as depth address output signals Dep_ADDR_out. Forexample, the first to n-th depth address output circuits 530_1 to 530_nmay correspond to first to n-th depths, respectively, and thus, outputsequentially stored addresses.

The enable/reset signal generator 550 may provide an enable signal ENSto each of the first to n-th depth address output circuits 530_1 to530_n such that the respective first to n-th depth address outputcircuits 530_1 to 530_n sequentially store and output addresses. In anembodiment, the enable/reset signal generator 550 may generate theenable signal ENS based on the internal commands INTN_CMDs. Also, when amemory device is powered off or receives a reset signal from theoutside, the enable/reset signal generator 550 may provide a resetsignal RST for resetting an address stored in each of the first to n-thdepth address output circuits 530_1 to 530_n to each of the first ton-th depth address output circuits 530_1 to 530_n

FIG. 8 illustrates an embodiment of the bubble interval detector 510 ofFIG. 7, and FIG. 9 illustrates an embodiment of the depth address outputcircuit 530_m of FIG. 7. Here, each of a first internal commandINTN_CMD1_a and a second internal command INTN_CMD2_a may be a signalgenerated based on a first command for controlling a memory operation ofa target bank of a first bank group, a burst length signal BLS is asignal indicating whether the first command is a command for performinga data burst operation having a burst length of reference bits or more,and a third internal command INTN_CMD2_a is a signal generated inresponse to a second command for controlling a memory operation of atarget bank of a second bank group.

Referring to FIG. 8, the bubble interval detector 510 may include abubble interval detection start unit 511, delay units 512 a to 512 d, asignal detector 513, drivers 514 a to 514 d, and a latch 515. Thedrivers 514 a to 514 d may be circuits configured to improvecharacteristics of respective signals and align edges of the respectivesignals. Also, each of the delay units 512 a to 512 d may delay a signalby as much as a second clock cycle (e.g., 2 clocks).

Operation of setting a detection signal BD_RS will now be described. Thebubble interval detection start unit 511 may receive the first internalcommand INTN_CMD1_a and the burst length signal BLS and start to detecta bubble interval. In an example, when the burst length signal BLS is ahigh-level signal indicating that the first command is a command forperforming a data burst operation having a burst length of referencebits or more, the bubble interval detection start unit 511 may providethe first internal command INTN_CMD1_a to the delay unit 512 a. Thedelay unit 512 a may delay the first internal command INTN_CMD1_a by asmuch as the second clock cycle and provide the delayed first internalcommand INTN_CMD1_a to the signal detector 513.

When the bubble interval detection start unit 511 receives the thirdinternal command INTN_CMD2_a after the second clock cycle from a timepoint at which the bubble interval detection start unit 511 receives thefirst internal command INTN_CMD1_a, the signal detector 513 may providethe delayed first internal command INTN_CMD1_a to the delay unit 512 b,and the delay unit 512 b may delay the delayed first internal commandINTN_CMD2_a by as much as the second clock cycle and provide the delayedfirst internal command INTN_CMD2_a to the latch 515.

In this case, the latch 515 may output a high-level detection signalBD_RS indicating that a bubble interval is not detected. In anothercase, when the bubble interval detection start unit 511 does not receivethe third internal command INTN_CMD2_a after the second clock cycle fromthe time point at which the first internal command INTN_CMD1_a isreceived, the signal detector 513 may not provide the delayed firstinternal command INTN_CMD1_a to the delay unit 512 b, and the latch 515may output a low-level detection signal BD_RS indicating that the bubbleinterval is detected.

The operation of resetting the detection signal BD_RS will now bedescribed. After a first clock cycle from a time point at which thebubble interval detection start unit 511 receives the first internalcommand INTN_CMD1_a, the second internal command INTN_CMD1_b received bythe bubble interval detector 510 may be delayed by as much as the firstclock cycle by the delay units 512 c and 512 d, and the delay unit 512 dmay provide the delayed second internal command INTN_CMD1_b to the latch515. In this case, the latch 515 may reset the detection signal BD_RS toan initial level (e.g., a low level). The bubble interval detector 510may be differently configured in another embodiment.

Referring to FIG. 9, the depth-based address output unit 530 may includea plurality of depth address output circuits 530_1 to 530_n. An m-thdepth address output circuit 530_m may include a storage path selector532_m and an address storage unit 534_m. The m-th storage path selector532_m may include first to third selection circuits SC1 to SC3. In anembodiment, the storage path selector 532_m may be enabled based on anm-th enable signal ENS[m] and receive a first internal commandINTN_CMD1_a or a second internal command INTN_CMD2_b along with adetection signal RD_RS and a detection inverted signal /RD_RS. The m-thaddress storage unit 534 m may include a multiplexer MUX including aplurality of switch elements, for example, switch elements SW1 to SW3,and a latch LAT. The multiplexer MUX may select a storage path based ona selection signal output by the storage path selector 532_m. The latchLAT may store an address through the selected storage path.Subsequently, the latch LAT may output the stored address to an m-thdepth address output signal Dep_ADDR_out[m]. Configuration of the m-thdepth address output circuit 530_m may be applied to other depth addressoutput circuits 530_1 to 530_n.

In an embodiment, when the storage path selector 532_m receives thefirst internal command INTN_CMD1_a, the first selection circuit SC1 maygenerate a high-level first selection signal A, and the second selectioncircuit SC2 and the third selection circuit SC3 may generate a low-levelsecond selection signal C and a low-level third selection signal E,respectively. The address storage unit 534_m may store an externallyreceived address ADDR in the latch LAT based on the first selectionsignal A, and output the stored address ADDR as the depth address outputsignal Dep_ADDR_out[m].

When the storage path selector 532_m receives the second internalcommand INTN_CMD1_b and a low-level detection signal BD_RS, the secondselection circuit SC2 may generate a high-level second selection signalC. and the first selection circuit SC1 and the third selection circuitSC3 may generate a low-level first selection signal A and a low-levelthird selection signal E, respectively.

The address storage unit 534_m may store an m−1-th depth address outputsignal Dep_ADDR_out[m−1] output by an m−1 depth address output circuit530_m−1 in the latch LAT in response to the second selection signal C,and output the stored m−1-th depth address output signalDep_ADDR_out[m−1] as the depth address output signal Dep_ADDR_out[m].

Finally, when the storage path selector 532_m receives the secondinternal command INTN_CMD1_b and a high-level detection signal BD_RS,the third selection circuit SC3 may generate a high-level thirdselection signal E, and the first selection circuit SC1 and the secondselection circuit SC2 may generate a low-level first selection signal Aand a low-level second selection signal C, respectively. The addressstorage unit 534_m may store an m−2-th depth address output signalDep_ADDR_out[m−2] output by an m−2-th depth address output circuit530_m−2 in the latch LAT in response to the third selection signal E andoutput the stored m−2-th depth address output signal Dep_ADDR_out[m−2]as the depth address output signal Dep_ADDR_out[m]. Subsequently, thelatch LAT may receive an m-th reset signal RST[m] and be reset. Thedepth-based address output unit 530 may have a different configurationin another embodiment.

FIG. 10A illustrates an embodiment for controlling the storage andoutput of a first address ADDR1 of a depth-based address output unit 530when a bubble interval is in a data burst interval corresponding to afirst command WR1 according to an embodiment. FIG. 10B illustrates anembodiment of a timing diagram for operating the depth-based addressoutput unit 530 of FIG. 10A.

Referring to FIG. 10A, the depth-based address output unit 530 mayinclude first to fourth depth address output circuit 530_1 to 530_4.Referring to FIG. 10B, since the first write command WR1, a firstaddress ADDR1, and internal commands INTN_WR1_a and INTN_WR1_b aredescribed above in detail with reference to FIG. 5A, operations of thedepth-based address output unit 530 based on enable signals ENS[1] toENS[4] will be described below.

Referring back to FIGS. 10A and 10B, the first depth address outputcircuit 530_1 may be enabled in time points t1 to t5 based on a firstenable signal ENS[1], and receive a first internal write commandINTN_WR1_a in a time point t3. The depth address output circuit 530_1may receive the first address ADDR1 from the outside based on the firstinternal write command INTN_WR1_a and store the first address ADDR1. Thefirst depth address output circuit 530_1 may output the first addressADDR1 as a first depth address output signal Dep_ADDR_out[1] to enable amemory operation in response to the first internal write commandINTN_WR1_a.

After the time point t5, the first depth address output circuit 530_1may be disabled. The second depth address output circuit 530_2 may beenabled between the time point t5 and the time point t9 based on asecond enable signal ENS[2]. The second depth address output circuit530_2 may receive a second internal write command INTN_WR1_b in the timepoint t7. The second depth address output circuit 530_2 may store thefirst address ADDR1 stored in the first depth address output circuit530_1 based on the second internal write command INTN_WR1_b and ahigh-level (H) detection signal BD_RS. The second depth address outputcircuit 530_2 may output the first address ADDR1 to the second depthaddress output signal Dep_ADDR_out[2]) to enable a memory operation inresponse to the second internal write command INTN_WR1_b.

After the time point t9, the second depth address circuit 530_2 may bedisabled. The third depth address output circuit 530_3 may be enabledbased on the third enable signal ENS[3], receive the next internalcommand, and stand by to store and output an address corresponding tothe next internal command.

FIG. 11A illustrates an embodiment for controlling the storage andoutput of a first address ADDR1 of a depth-based address output unit 530when a bubble interval is not in a data burst interval corresponding toa first command WR1 according to an embodiment. FIG. 11B illustrates anembodiment of a timing diagram of an operation of the depth-basedaddress output unit 530 of FIG. 11A.

Referring to FIG. 11A, the depth-based address output unit 530 mayinclude first to fourth depth address output circuits 530_1 to 530_4.Referring to FIG. 10B, since the first write command WR1, the firstaddress ADDR1, and internal commands INTN_WR1_a and INTN_WR1_b aredescribed above in detail with reference to FIG. 5A, operations of thedepth-based address output unit 530 in response to enable signals ENS[1]to ENS[4] will be described below.

Referring back to FIGS. 11A and 11B, the first depth address outputcircuit 530_1 may be enabled based on a first enable signal ENS[1]between a time point t2 and a time point t4, and receive a firstinternal write command INTN_WR1_a in the time point 13. The depthaddress output circuit 530_1 may receive the first address ADDR1 fromthe outside and store the first address ADDR1 based on the firstinternal write command INTN_WR1_a. The first depth address outputcircuit 530_1 may output the first address ADDR1 as a first depthaddress output signal Dep_ADDR_out[1] to enable a memory operation basedon the first internal write command INTN_WR1_a.

After the time point t4, the first depth address output circuit 530_1may be disabled. The second depth address output circuit 530_2 may beenabled between the time point t4 and the time point t6 based on asecond enable signal ENS[2]. The second depth address output circuit530_2 may receive a third internal write command INTN_WR2_a in the timepoint t5. The second depth address output circuit 530_2 may receive asecond address ADDR2 from the outside and store the second address ADDR2based on the third internal write command INTN_WR2_a. The second depthaddress output circuit 530_2 may output the second address ADDR2 as asecond depth address output signal Dep_ADDR_out[2] to enable a memoryoperation based on the third internal write command INTN_WR2_a.

After the time point t6, the second depth address output circuit 530_2may be disabled. The third depth address output circuit 530_3 may beenabled between the time point t6 and the time point t8 based on a thirdenable signal ENS[3]. The third depth address output circuit 530_3 mayreceive a second internal write command INTN_WR1_b in the time point t7.The third depth address output circuit 530_3 may store the first addressADDR1 stored in the first depth address output circuit 530_1 based onthe second internal write command INTN_WR1_b and a low-level (L)detection signal BD_RS. The third depth address output circuit 530_3 mayoutput the first address ADDR1 as a third depth address output signalDep_ADDR_out[3] to enable a memory operation based on the secondinternal write command INTN_WR1_b.

After the time point t8, the third depth address output circuit 530_3may be disabled. The fourth depth address output circuit 530_4 may beenabled between the time point t8 and the time point t10 based on afourth enable signal ENS[4]. The fourth depth address output circuit530_4 may receive a fourth internal write command INTN_WR2_b in the timepoint t9. The fourth depth address output circuit 530_4 may store thesecond address ADDR2 stored in the second depth address output circuit530_2 based on the fourth internal write command INTN_WR2_b and thelow-level (L) detection signal BD_RS. The fourth depth address outputcircuit 5304 may output the second address ADDR2 as a fourth depthaddress output signal Dep_ADDR_out[4] to enable a memory operation basedon the fourth internal write command INTN_WR2_b.

FIGS. 12A and 12B illustrates embodiments of timing diagrams foroperating a memory device in a read operation. Referring to FIG. 12A, awrite latency ‘WR latency’ may be present in a write operation based ona write command as shown in FIG. 5A. A read latency may not be presentin a read operation based on a read command.

Thus, an internal command generator may receive a first read commandRD1, output a first internal read command INTN_RD1_a to a first targetbank in a time point t1, and output a second internal read commandINTN_RD1_b to a first target bank in a time point t5, which is a tCCDinterval INTV_tCCD after the time point t1. In this case, an address I/Ocircuit may output a first address ADDR3 in each of the time points t1and t5 in accordance with the time points when the internal commandgenerator outputs the first internal read command INTN_RD1_a and thesecond internal read command INTN_RD1_b to the first target bank. In anembodiment, a data clock WCK may be a signal based on a clock receivedfrom the outside (e.g., a memory controller).

In addition, referring to FIG. 12B, the internal command generator mayfurther receive a second read command RD2, output a third internal readcommand INTN_RD2_a to a second target bank in the time point t3, andoutput a fourth internal read command INTN_RD2_b to the second targetbank in the time point t5, which is a tCCD interval INTV_tCCD after thetime point t3. In this case, the address I/O circuit may output a secondaddress ADDR4 to the second target bank in each of the time points t3and t7 in accordance with the time points when the internal commandgenerator outputs the third internal read command INTN_RD2_a and thefourth internal read command INTN_RD2_b to the second target bank.

FIG. 13 illustrates an embodiment of an address I/O circuit 700configured to operate in consideration of a read operation devoid of aread latency.

Referring to FIG. 13, the address I/O circuit 700 may include a bubbleinterval detector 710, a depth-based address output unit 730, and anenable/reset signal generator 750. The bubble interval detector 710 mayreceive internal read commands INTN_RDs and detect a bubble intervalbased on patterns of the internal read commands INTN_RDs. The bubbleinterval detector 710 may generate a detection signal BD_RS′ based on adetection result of the bubble interval and provide the detection signalBD_RS' to the depth-based address output unit 730. The depth-basedaddress output unit 730 may include a read address latch circuit 731 anda depth read address output circuit 732.

The read address latch circuit 731 may store addresses ADDRs receivedbased on the internal commands INTN_CMDs. Specifically, the read addresslatch circuit 731 may change positions in which the addresses ADDRs arestored, based on the internal read commands INTN_RDs. The depth readaddress output circuit 732 may select an address required for a readoperation, from among the addresses ADDRs stored in the read addresslatch circuit 731, based on the detection signal BD_RS′, and output theselected address as a depth read address output signal Dep_RD_ADDR_out.

When the read operation is performed, the enable/reset signal generator750 may generate an enable signal ENS' for enabling the depth-basedaddress output unit 730. In an embodiment, the enable/reset signalgenerator 750 may generate the enable signal ENS' based on the internalread commands INTN_RDs. Also, when a memory device is powered off orreceives a reset signal from the outside, the enable/reset signalgenerator 750 may provide a reset signal RST to the depth-based addressoutput unit 730 and reset the addresses ADDRs stored in the read addresslatch circuit 731.

FIG. 14 illustrates an embodiment of the bubble interval detector 710 ofFIG. 13 and an embodiment of the depth-based address output unit 730 ofFIG. 13.

Referring to FIG. 14, the bubble interval detector 710 may include abubble interval detection start unit 711, delay units 712 a to 712 c, asignal detector 713, drivers 714 a to 714 c, and a latch 715. Since thenumber of the delay units 712 a to 712 c connected to a reset terminalof the latch 715 in the bubble interval detector 710 is one less than inthe bubble interval detector 510 of FIG. 8, a time point at which adetection signal BD_RS' of the latch 715 is set may be by as much as asecond clock cycle earlier than a time point at which the detectionsignal BD_RS of the latch 515 of FIG. 8 is reset. For example, the timepoint at which the detection signal BD_RS' of the bubble intervaldetector 710 is set may be controlled to be different from the timepoint at which the detection signal BD_RS of the bubble intervaldetector 510 of FIG. 8 is reset. Operations of the bubble intervaldetector 710 may be similar to operations of the bubble intervaldetector 510 of FIG. 8. The configuration of the bubble intervaldetector 710 may be different in another embodiment.

Referring further to FIG. 15, the depth-based address output unit 730may include a read address latch circuit 731 and a depth read addressoutput circuit 732. The read address latch circuit 731 may include aplurality of switch elements SW1 to SW4 and a plurality of latches LAT1to LAT4. The read address latch circuit 731 may change a latch in whichan address ADDR is stored, based on an internal read command INTN_RD_a.The internal read command INTN_RD_a may be a firstly generated or outputinternal read command, from among internal read commands correspondingto a predetermined read command. For example, from among a firstinternal read command a second internal read command, which correspondto a first read command, and a third internal read command and a fourthinternal read command, which correspond to a second read command, theread address latch circuit 731 may change the latch in which the addressADDR is stored, based on the first internal command and the thirdinternal command.

The depth read address output circuit 732 may include a multiplexer MUXand a driver DRV. As described above with reference to FIG. 1, the depthread address output circuit 732 may output the address ADDR to banks. Aspecific output method of the depth read address output circuit 732according to an embodiment will now be described.

The depth read address output circuit 732 may be connected to outputterminals of a second latch LAT2 and a fourth latch LAT4 of the readaddress latch circuit 731 and receive an address ADDR_PRE stored in thesecond latch LAT2 and an address ADDR_LAT stored in the fourth latchLAT4. The depth read address output circuit 732 may directly output thereceived address ADDR as the depth read address output signalDep_RD_ADDR_out based on an enable signal ENS, or select any one of anaddress ADDR_PRE stored in the second latch LAT2 and an address ADDR_LATstored in the fourth latch LAT4 based on the enable signal ENS and thedetection signal BD_RS' and output the selected address as the depthread address output signal Dep_RD_ADDR_out. The configuration of thedepth-based address output unit 730 may be different in anotherembodiment.

FIG. 16 illustrates an embodiment of an operation of the depth-basedaddress output unit 730 corresponding to the timing diagram of FIG. 12B.Referring to FIGS. 12B and 13 to 16, to begin, when the read addresslatch circuit 731 receives a first address ADDR3 and a first internalread command INTN_RD1_a, the read address latch circuit 731 maysequentially store the first address ADDR3 in a first latch LAT1 and thesecond latch LAT2. Also, since the bubble interval detector 710 receivesonly the first internal read command INTN_RD1_a, the bubble intervaldetector 710 may output an initial-level (e.g., low-level) detectionsignal BD_RS′. The depth read address output circuit 732 may directlyselect the first address ADDR3 and output the first address ADDR3 as adepth read address output signal Dep_RD_ADDR_out.

When the read address latch circuit 731 receives a second address ADDR4and a third internal read command INTN_RD2_a, the read address latchcircuit 731 may sequentially store a second address ADDR4 in the firstlatch LAT1 and the second latch LAT2, and sequentially the first addressADDR3 in the third latch LAT3 and the fourth latch LAT4. Also, since thebubble interval detector 710 receives the third internal read commandINTN_RD2_a after a second clock cycle from a time point at which thebubble interval detector 710 receives the first internal read commandINTN_RD1_a, the bubble interval detector 710 may output a high-leveldetection signal BD_RS′. The depth read address output circuit 732 maydirectly select the second address ADDR4 and output the second addressADDR4 as the depth read address output signal Dep_RD_ADDR_out.

When the read address latch circuit 731 receives the second internalread command INTN_RD1_b, the read address latch circuit 731 may maintaina storage state of each of the first to fourth latches LAT1 to LAT4.Although the bubble interval detector 710 receives the second internalread command INTN_RD1_b, the bubble interval detector 710 may output adetection signal BD_RS′, which is maintained at a high level, due to adelay unit 712. The depth read address output circuit 732 may select andoutput the address ADDR_LAT stored in the fourth latch LAT4 based on thehigh-level detection signal BD_RS′. That is, the depth read addressoutput circuit 732 may output the first address ADDR3 stored in thefourth latch LAT4 as the depth read address output signalDep_RD_ADDR_out to perform a read operation in response to the secondinternal read command INTN_RD1_b.

When the read address latch circuit 731 receives the fourth internalread command INTN_RD2_b, the read address latch circuit 731 may maintaina storage state of each of the first to fourth latches LAT1 to LAT4.Since the second clock cycle has elapsed after the bubble intervaldetector 710 receives the second internal read command INTN_RD1_b, theread address latch circuit 731 may output a detection signal BD_RS′,which is reset to a low level. The depth read address output circuit 732may select and output the address ADDR_PRE stored in the second latchLAT2 based on the low-level detection signal BD_RS′. That is, the depthread address output circuit 732 may output the second address ADDR4 as adepth read address output signal Dep_RD_ADDR_out to enable a readoperation based on the fourth internal read command INTN_RD2_b.

FIG. 17 illustrates an embodiment of a memory system 1000 which mayinclude a memory controller 1200 and a memory module 1400. The memorymodule 1400 may include at least one memory chip 1800, each of which mayinclude a memory cell array, and a buffer chip 1620 for transceivingsignals between the at least one memory chip 1800 and the memorycontroller 1200 or manage a memory operation on the memory chips 1800.The memory chips 1800 of the memory module 1400 may be divided into afirst rank R1 and a second rank R2. Each of the at least one memory chip1800 may include an address I/O circuit AIDC to which the embodimentsdescribed with reference to FIGS. 1 to 16 are applied to perform amemory operation.

Although FIG. 17 illustrates an example in which part of function of thememory controller 1200 is performed in a load-reduced dual in-linememory module (LRDIMM)-type memory module, the inventive concept is notlimited thereto. For example, a fully buffered DIMM (FBDIMM)-type memorymodule may be applied to the memory module 1400, and an advanced memorybuffer (AMB) chip may be mounted as a buffer chip on the memory module1400. In addition, another type of memory module may be applied to thememory module 1400, and the at least part of the function of the memorycontroller 1200 may be performed in the memory module 1400.

FIG. 18 illustrates an embodiment of a semiconductor package 2000including a stack structure having a plurality of layers. Referring toFIG. 18, the semiconductor package 2000 may include a plurality oflayers LA1 to LAn. Each of first to n−1-th layers LA1 to LAn may be amemory layer (or a memory chip) including a plurality of memory bankgroups 2100.

Each of the memory bank groups 2100 may include a plurality of banks,each of which may include a memory cell array configured to store data,a row decoder, a column decoder, and a sense amplifier. The n-th layerLAn)

may be a buffer layer. In the semiconductor package 2000, the stackedlayers LA1 to LAn may be connected to one another throughthrough-silicon vias (TSVs) 2300. The buffer layer LAn may communicatewith an external memory controller and the memory layers LA1 to LAn−1,and route transceiving signals between the memory layers LA1 to LAn−1and the external memory controller. The buffer layer LAn may include anaddress I/O circuit 2200. The embodiments described with reference toFIGS. 1 to 16 may be applied to the address I/O circuit 2200 to performa memory operation.

FIG. 19 illustrates an embodiment of a semiconductor package 3000including a stack semiconductor chip. Referring to FIG. 19, thesemiconductor package 3000 may be a memory module including at least onestack semiconductor chip 3300 and a System-on-Chip (SoC) 3400, which aremounted on a package substrate 3100 (e.g., a printed circuit board(PCB)). An interposer 3200 may be optionally further provided on thepackage substrate 3100.

The stack semiconductor chip 3300 may be embodied by a Chip-on-Chip(CoC). The stack semiconductor chip 3300 may include at least one memorychip 3320 stacked on a buffer chip 3310 (e.g., a logic chip). The bufferchip 3310 and the at least one memory chip 3320 may be connected to eachother by through-silicon vias (TSVs). The buffer chip 3320 may includean address I/O circuit to which the embodiments described with referenceto FIGS. 1 to 16 are applied to perform a memory operation. In anexample, the stack semiconductor chip 3300 may be a high-bandwidthmemory (HBM) having a bandwidth of about 500 GB/sec to about 1 TB/sec orhigher.

The methods, processes, and/or operations described herein may beperformed by code or instructions to be executed by a computer,processor, controller, or other signal processing device. The computer,processor, controller, or other signal processing device may be thosedescribed herein or one in addition to the elements described herein.Because the algorithms that form the basis of the methods (or operationsof the computer, processor, controller, or other signal processingdevice) are described in detail, the code or instructions forimplementing the operations of the method embodiments may transform thecomputer, processor, controller, or other signal processing device intoa special-purpose processor for performing the methods herein.

The generators, controllers, outputs, interfaces, modules, detectors,decoders, delays and other units, latches, and other signal generating,signal providing, and signal processing features of the embodimentsdisclosed herein may be implemented in non-transitory logic which, forexample, may include hardware, software, or both. When implemented atleast partially in hardware, the generators, controllers, outputs,interfaces, modules, detectors, decoders, delays and other units,latches, and other signal generating, signal providing, and signalprocessing features may be, for example, any one of a variety ofintegrated circuits including but not limited to an application-specificintegrated circuit, a field-programmable gate array, a combination oflogic gates, a system-on-chip, a microprocessor, or another type ofprocessing or control circuit.

When implemented in at least partially in software, the generators,controllers, outputs, interfaces, modules, detectors, decoders, delaysand other units, latches, and other signal generating, signal providing,and signal processing features may include, for example, a memory orother storage device for storing code or instructions to be executed,for example, by a computer, processor, microprocessor, controller, orother signal processing device. The computer, processor, microprocessor,controller, or other signal processing device may be those describedherein or one in addition to the elements described herein. Because thealgorithms that form the basis of the methods (or operations of thecomputer, processor, microprocessor, controller, or other signalprocessing device) are described in detail, the code or instructions forimplementing the operations of the method embodiments may transform thecomputer, processor, controller, or other signal processing device intoa special-purpose processor for performing the methods described herein.

The various operations of methods described above may be performed byany suitable means capable of performing the operations, such as varioushardware and/or software component(s), circuits, and/or module(s).

The software may comprise an ordered listing of executable instructionsfor implementing logical functions, and can be embodied in any“processor-readable medium” for use by or in connection with aninstruction execution system, apparatus, or device, such as a single ormultiple-core processor or processor-containing system.

The blocks or steps of a method or algorithm and functions described inconnection with the embodiments disclosed herein may be embodieddirectly in hardware, in a software module executed by a processor, orin a combination of the two. If implemented in software, the functionsmay be stored on or transmitted over as one or more instructions or codeon a tangible, non-transitory computer-readable medium. A softwaremodule may reside in Random Access Memory (RAM), flash memory, Read OnlyMemory (ROM), Electrically Programmable ROM (EPROM), ElectricallyErasable Programmable ROM (EEPROM), registers, hard disk, a removabledisk, a CD ROM, or any other form of storage medium known in the art.

In accordance with one or more of the aforementioned embodiments, due toa frequency difference between the reference clock and the data clock,an interval (e.g., a bubble interval) in which data is not transceivedto and from a pad may occur during a memory operation (e.g., a databurst operation corresponding to a command) of the memory device. Toimprove efficiency of the memory operation and performance of the memorysystem, the memory system may perform a memory operation for reducing orminimizing a bubble interval. For example, an address I/O circuit maycontrol a circuit (that stores an address when there is a bubbleinterval in the data burst operation interval corresponding to areceived command) to be different from a circuit that stores the addresswhen there is not the bubble interval. The address I/O circuit mayoutput the stored address to the bank group BG in accordance with a timepoint at which the internal command is output to the bank group BG. Dueto the above-described operations of the address I/O circuit, the bubbleinterval may be reduced. As a result, the memory device may performefficient memory operations.

Example embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation. In someinstances, as would be apparent to one of skill in the art as of thefiling of the present application, features, characteristics, and/orelements described in connection with a particular embodiment may beused singly or in combination with features, characteristics, and/orelements described in connection with other embodiments unless otherwiseindicated. Accordingly, various changes in form and details may be madewithout departing from the spirit and scope of the embodiments set forthin the claims.

What is claimed is:
 1. A memory device, comprising: a first bank group;a second bank group, each of the first and second bank groups includinga plurality of banks; an internal command generator to generate a firstinternal command and a second internal command based on a first commandfrom a memory controller, the first command to control a memoryoperation of a first target bank in the first bank group, the internalcommand generator to output the first internal command and the secondinternal command to the first target bank; and an address input/output(I/O) circuit to receive a first address corresponding to the firstcommand, select a storage path of the first address based on whetherthere is a bubble interval in a data burst operation intervalcorresponding to the first command, control output of the first addressin accordance with a time point at which each of the first internalcommand and the second internal command is output, and store the firstaddress in the address I/O circuit, wherein the address I/O circuitincludes a bubble interval detector to detect the bubble interval basedon whether a second command to control a memory operation of a secondtarget bank in the second bank group is received from the memorycontroller within a first clock cycle from a time point at which thememory device receives the first command, the bubble interval detectorto generate a detection signal.
 2. The memory device as claimed in claim1, wherein a frequency of data clocks synchronized in a data burstoperation is greater than a frequency of reference clocks synchronizedin the memory operation.
 3. The memory device as claimed in claim 1,wherein: when a burst length of a data burst operation corresponding tothe first command is 2n bits, which is equal to or higher than referencebits, each of a burst length of a data burst operation corresponding tothe first internal command and a burst length of a data burst operationcorresponding to the second internal command is n bits, where n is aninteger equal to or more than
 2. 4. The memory device as claimed inclaim 1, wherein a burst length of a data burst operation correspondingto the first command is equal to or different from a burst length of adata burst operation corresponding to a second command received by thememory device after the memory device receives the first command.
 5. Thememory device as claimed in claim 1, wherein: the data burst operationinterval corresponding to the first command includes a first data burstoperation interval corresponding to the first internal command and asecond data burst operation interval corresponding to the secondinternal command, the bubble interval is an interval for which a databurst operation is not performed between the first data burst operationinterval and the second data burst operation interval.
 6. The memorydevice as claimed in claim 1, wherein: the first clock cycle includes atime interval based on a core cycle to perform a memory operation basedon the first internal command, and the internal command generator is tooutput the second internal command to the first target bank after thefirst clock cycle, from a time point at which the internal commandgenerator outputs the first internal command to the first target bank.7. The memory device as claimed in claim 1, wherein: the internalcommand generator is to generate a third internal command based on thesecond command at a time point at which the second command is received,and when the third internal command is received after a second clockcycle from a time point at which the first internal command is received,the bubble interval detector is to set the detection signal to a firstlevel indicating that the bubble interval is detected, after the secondclock cycle from a time point at which the third internal command isreceived.
 8. The memory device as claimed in claim 7, wherein the secondclock cycle is a time interval of the bubble interval.
 9. The memorydevice as claimed in claim 8, wherein: when the second internal commandis received, the bubble interval detector is to reset the detectionsignal to a second level after the first clock cycle from the time pointat which the second internal command is received.
 10. The memory deviceas claimed in claim 1, wherein: the address I/O circuit includes adepth-based address output including first to third depth address outputcircuits to store respective addresses therein, and the first to thirddepth addresses output circuits are to sequentially output therespective addresses stored therein to any one of the banks.
 11. Thememory device as claimed in claim 10, wherein, when the first internalcommand is received, the depth-based address output is to: store thefirst address received from the memory controller in the first depthaddress output circuit, and store the first address stored in the firstdepth address output circuit, in one of the second depth address outputcircuit and the third depth address output circuit, based on thedetection signal.
 12. The memory device as claimed in claim 11, wherein,when the detection signal is at a first level indicating that the bubbleinterval is detected, the depth-based address output is to: store thefirst address stored in the first depth address output circuit in thethird depth address output circuit, and store a second addresscorresponding to the second command in the second depth address outputcircuit.
 13. The memory device as claimed in claim 11, wherein: when thedetection signal is at a second level indicating that the bubbleinterval is not detected, the depth-based address output is to store thefirst address stored in the first depth address output circuit in thesecond depth address output circuit.
 14. The memory device as claimed inclaim 1, wherein the memory device is to operate in an on-the-fly modeto perform a data burst operation having a variable burst length.
 15. Amemory device, comprising: a first bank group; a second bank group, eachof the first and second bank groups including a plurality of banks; aninternal command generator to generate a first internal command and asecond internal command based on a first command received from a memorycontroller, the first command to control a memory operation of a firsttarget bank of the first bank group, generate a third internal commandbased on a second command received from the memory controller to controla memory operation of a second target bank of the second bank groupafter the first command, and output the first to third internalcommands; and an address input/output (I/O) circuit to receive the firstto third internal commands, receive from the memory controller a firstaddress corresponding to the first command and a second addresscorresponding to the second command, and store the first address and thesecond address using a storage path selected based on whether the thirdinternal command is received, within a first clock cycle from a timepoint at which the first internal command is received, wherein: theaddress I/O circuit includes first to third depth address outputcircuits to store respective addresses therein, and the first to thirddepth address output circuits are to sequentially output the respectiveaddresses stored therein to one of the banks.
 16. The memory device asclaimed in claim 15, wherein: when the third internal command isreceived within the first clock cycle from the time point at which thefirst internal command is received, the address I/O circuit is to storethe first address received from the memory controller in the first depthaddress output circuit and output the first address to the first targetbank through the first depth address output circuit in accordance with atime point at which the internal command generator outputs the firstinternal command to the first target bank, the address I/O circuit is tostore, in the second depth address output circuit, the second addressreceived from the memory controller and output the second address to thesecond target bank through the second depth address output circuit inaccordance with a time point at which the internal command generatoroutputs the third internal command to the second target bank, and theaddress I/O circuit is to store the first address stored in the firstdepth address output circuit in the third depth address output circuitand output the first address to the first target bank through the thirddepth address output circuit in accordance with a time point at whichthe internal command generator outputs the second internal command tothe first target bank of the first bank group.
 17. The memory device asclaimed in claim 15, wherein: when the third internal command is notreceived within the first clock cycle from the time point at which thefirst internal command is received, the address I/O circuit is to storethe first address received from the memory controller in the first depthaddress output circuit and output the first address to the first targetbank through the first depth address output circuit in accordance with atime point at which the internal command generator outputs the firstinternal command to the first target bank, the address I/O circuit is tostore the first address stored in the first depth address output circuitin the second depth address output circuit and output the first addressto the first target bank through the second depth address output circuitin accordance with a time point at which the internal command generatoroutputs the second internal command to the first target bank, and theaddress I/O circuit is to store the second address received from thememory controller in the third depth address output circuit and outputthe second address to the second target bank through the third depthaddress output circuit in accordance with a time point at which theinternal command generator outputs the third internal command to thesecond target bank.
 18. A non-transitory computer-readable mediumcomprising code, which, when executed by a processor, causes theprocessor to: generate, by an internal command generator, a firstinternal command and a second internal command based on a first commandfrom a memory controller, the first command to control a memoryoperation of a first target bank in a first bank group; receive, by anaddress input/output (I/O) circuit, a first address corresponding to thefirst command; detect a bubble interval based on whether a secondcommand to control a memory operation of a second target bank in asecond bank group is received from the memory controller within a firstclock cycle from a time point at which the internal command generatorreceives the first command; generate a detection signal by a bubbleinternal detector of the address I/O circuit when the bubble interval isdetected; select a storage path of the first address based on thedetection signal; control output of the first address in accordance witha time point at which each of the first internal command and the secondinternal commands is output to the first target bank; and store thefirst address in the address I/O circuit.